`include "router_behav.v"
module aib_mac_ch_tb;
    reg mclk;
    reg nclk;
    reg rst;
    //add[2:0]  12.5
    reg [2:0] L_CX;
    reg [2:0] L_CY;
    wire [639:0] l_data_in_f;
    wire [639:0] l_data_out_f;
    wire l_m_wr_clk;
    wire l_m_rd_clk;
    wire l_m_ns_fwd_clk;
    wire l_m_fs_fwd_clk;
    wire l_ns_mac_rdy;
    wire l_fs_mac_rdy;
    wire l_ns_adapter_rstn;
    wire l_ms_tx_dcc_dll_lock_req;
    wire l_ms_rx_dcc_dll_lock_req;
    wire l_sl_tx_dcc_dll_lock_req;
    wire l_sl_rx_dcc_dll_lock_req;
    wire l_ms_tx_transfer_en;
    wire l_ms_rx_transfer_en;
    wire l_sl_tx_transfer_en;
    wire l_sl_rx_transfer_en;
    wire [127:0] l_i_data0_0;
    wire l_i_valid0_0;
    wire l_o_yummy0_0;
    wire [127:0] l_o_data0_0;
    wire l_o_valid0_0;
    wire l_i_yummy0_0;
    wire [127:0] l_i_data1_0;
    wire l_i_valid1_0;
    wire l_o_yummy1_0;
    wire [127:0] l_o_data1_0;
    wire l_o_valid1_0;
    wire l_i_yummy1_0;
    wire [127:0] l_i_data0_1;
    wire l_i_valid0_1;
    wire l_o_yummy0_1;
    wire [127:0] l_o_data0_1;
    wire l_o_valid0_1;
    wire l_i_yummy0_1;
    wire [127:0] l_i_data1_1;
    wire l_i_valid1_1;
    wire l_o_yummy1_1;
    wire [127:0] l_o_data1_1;
    wire l_o_valid1_1;
    wire l_i_yummy1_1;
    wire [127:0] l_i_data0_2;
    wire l_i_valid0_2;
    wire l_o_yummy0_2;
    wire [127:0] l_o_data0_2;
    wire l_o_valid0_2;
    wire l_i_yummy0_2;
    wire [127:0] l_i_data1_2;
    wire l_i_valid1_2;
    wire l_o_yummy1_2;
    wire [127:0] l_o_data1_2;
    wire l_o_valid1_2;
    wire l_i_yummy1_2;
    wire [127:0] l_i_data0_3;
    wire l_i_valid0_3;
    wire l_o_yummy0_3;
    wire [127:0] l_o_data0_3;
    wire l_o_valid0_3;
    wire l_i_yummy0_3;
    wire [127:0] l_i_data1_3;
    wire l_i_valid1_3;
    wire l_o_yummy1_3;
    wire [127:0] l_o_data1_3;
    wire l_o_valid1_3;
    wire l_i_yummy1_3;
    //long wire
    wire [127:0] l_i_data0_4;
    wire l_i_valid0_4;
    wire l_o_yummy0_4;
    wire [127:0] l_o_data0_4;
    wire l_o_valid0_4;
    wire l_i_yummy0_4;
    wire [127:0] l_i_data1_4;
    wire l_i_valid1_4;
    wire l_o_yummy1_4;
    wire [127:0] l_o_data1_4;
    wire l_o_valid1_4;
    wire l_i_yummy1_4;
    //add 12.25
    wire [127:0] l_i_data0_5;
    wire l_i_valid0_5;
    wire l_o_yummy0_5;
    wire [127:0] l_o_data0_5;
    wire l_o_valid0_5;
    wire l_i_yummy0_5;
    wire [127:0] l_i_data1_5;
    wire l_i_valid1_5;
    wire l_o_yummy1_5;
    wire [127:0] l_o_data1_5;
    wire l_o_valid1_5;
    wire l_i_yummy1_5;

    //add[2:0]  12.5
    reg [2:0] R_CX;
    reg [2:0] R_CY;
    wire [639:0] r_data_in_f;
    wire [639:0] r_data_out_f;
    wire r_m_wr_clk;
    wire r_m_rd_clk;
    wire r_m_ns_fwd_clk;
    wire r_m_fs_fwd_clk;
    wire r_ns_mac_rdy;
    wire r_fs_mac_rdy;
    wire r_ns_adapter_rstn;
    wire r_ms_tx_dcc_dll_lock_req;
    wire r_ms_rx_dcc_dll_lock_req;
    wire r_sl_tx_dcc_dll_lock_req;
    wire r_sl_rx_dcc_dll_lock_req;
    wire r_ms_tx_transfer_en;
    wire r_ms_rx_transfer_en;
    wire r_sl_tx_transfer_en;
    wire r_sl_rx_transfer_en;
    wire [127:0] r_i_data0_0;
    wire r_i_valid0_0;
    wire r_o_yummy0_0;
    wire [127:0] r_o_data0_0;
    wire r_o_valid0_0;
    wire r_i_yummy0_0;
    wire [127:0] r_i_data1_0;
    wire r_i_valid1_0;
    wire r_o_yummy1_0;
    wire [127:0] r_o_data1_0;
    wire r_o_valid1_0;
    wire r_i_yummy1_0;
    wire [127:0] r_i_data0_1;
    wire r_i_valid0_1;
    wire r_o_yummy0_1;
    wire [127:0] r_o_data0_1;
    wire r_o_valid0_1;
    wire r_i_yummy0_1;
    wire [127:0] r_i_data1_1;
    wire r_i_valid1_1;
    wire r_o_yummy1_1;
    wire [127:0] r_o_data1_1;
    wire r_o_valid1_1;
    wire r_i_yummy1_1;
    wire [127:0] r_i_data0_2;
    wire r_i_valid0_2;
    wire r_o_yummy0_2;
    wire [127:0] r_o_data0_2;
    wire r_o_valid0_2;
    wire r_i_yummy0_2;
    wire [127:0] r_i_data1_2;
    wire r_i_valid1_2;
    wire r_o_yummy1_2;
    wire [127:0] r_o_data1_2;
    wire r_o_valid1_2;
    wire r_i_yummy1_2;
    wire [127:0] r_i_data0_3;
    wire r_i_valid0_3;
    wire r_o_yummy0_3;
    wire [127:0] r_o_data0_3;
    wire r_o_valid0_3;
    wire r_i_yummy0_3;
    wire [127:0] r_i_data1_3;
    wire r_i_valid1_3;
    wire r_o_yummy1_3;
    wire [127:0] r_o_data1_3;
    wire r_o_valid1_3;
    wire r_i_yummy1_3;
    //long wire
    wire [127:0] r_i_data0_4;
    wire r_i_valid0_4;
    wire r_o_yummy0_4;
    wire [127:0] r_o_data0_4;
    wire r_o_valid0_4;
    wire r_i_yummy0_4;
    wire [127:0] r_i_data1_4;
    wire r_i_valid1_4;
    wire r_o_yummy1_4;
    wire [127:0] r_o_data1_4;
    wire r_o_valid1_4;
    wire r_i_yummy1_4;

    wire [127:0] r_i_data0_5;
    wire r_i_valid0_5;
    wire r_o_yummy0_5;
    wire [127:0] r_o_data0_5;
    wire r_o_valid0_5;
    wire r_i_yummy0_5;
    wire [127:0] r_i_data1_5;
    wire r_i_valid1_5;
    wire r_o_yummy1_5;
    wire [127:0] r_o_data1_5;
    wire r_o_valid1_5;
    wire r_i_yummy1_5;
    aib_mac_ch l_aib_mac_ch(
    	.mclk(mclk),
        .nclk(nclk),
        .rst                    (rst                    ),
        .CX                    (L_CX                   ),
        .CY                    (L_CY                   ),
        .data_in_f              (l_data_in_f              ),
        .data_out_f             (l_data_out_f             ),
        .m_wr_clk               (l_m_wr_clk               ),
        .m_rd_clk               (l_m_rd_clk               ),
        .m_ns_fwd_clk           (l_m_ns_fwd_clk           ),
        .m_fs_fwd_clk           (l_m_fs_fwd_clk           ),
        .ns_mac_rdy             (l_ns_mac_rdy             ),
        .fs_mac_rdy             (l_fs_mac_rdy             ),
        .ns_adapter_rstn        (l_ns_adapter_rstn        ),
        .ms_tx_dcc_dll_lock_req (l_ms_tx_dcc_dll_lock_req ),
        .ms_rx_dcc_dll_lock_req (l_ms_rx_dcc_dll_lock_req ),
        .sl_tx_dcc_dll_lock_req (l_sl_tx_dcc_dll_lock_req ),
        .sl_rx_dcc_dll_lock_req (l_sl_rx_dcc_dll_lock_req ),
        .ms_tx_transfer_en      (l_ms_tx_transfer_en      ),
        .ms_rx_transfer_en      (l_ms_rx_transfer_en      ),
        .sl_tx_transfer_en      (l_sl_tx_transfer_en      ),
        .sl_rx_transfer_en      (l_sl_rx_transfer_en      ),
        .i_data0_0              (l_i_data0_0              ),
        .i_valid0_0             (l_i_valid0_0             ),
        .o_yummy0_0             (l_o_yummy0_0             ),
        .o_data0_0              (l_o_data0_0              ),
        .o_valid0_0             (l_o_valid0_0             ),
        .i_yummy0_0             (l_i_yummy0_0             ),

        .i_data1_0              (l_i_data1_0              ),
        .i_valid1_0             (l_i_valid1_0             ),
        .o_yummy1_0             (l_o_yummy1_0             ),
        .o_data1_0              (l_o_data1_0              ),
        .o_valid1_0             (l_o_valid1_0             ),
        .i_yummy1_0             (l_i_yummy1_0             ),

        .i_data0_1              (l_i_data0_1              ),
        .i_valid0_1             (l_i_valid0_1             ),
        .o_yummy0_1             (l_o_yummy0_1             ),
        .o_data0_1              (l_o_data0_1              ),
        .o_valid0_1             (l_o_valid0_1             ),
        .i_yummy0_1             (l_i_yummy0_1             ),

        .i_data1_1              (l_i_data1_1              ),
        .i_valid1_1             (l_i_valid1_1             ),
        .o_yummy1_1             (l_o_yummy1_1             ),
        .o_data1_1              (l_o_data1_1              ),
        .o_valid1_1             (l_o_valid1_1             ),
        .i_yummy1_1             (l_i_yummy1_1             ),

        .i_data0_2              (l_i_data0_2              ),
        .i_valid0_2             (l_i_valid0_2             ),
        .o_yummy0_2             (l_o_yummy0_2             ),
        .o_data0_2              (l_o_data0_2              ),
        .o_valid0_2             (l_o_valid0_2             ),
        .i_yummy0_2             (l_i_yummy0_2             ),

        .i_data1_2              (l_i_data1_2              ),
        .i_valid1_2             (l_i_valid1_2             ),
        .o_yummy1_2             (l_o_yummy1_2             ),
        .o_data1_2              (l_o_data1_2              ),
        .o_valid1_2             (l_o_valid1_2             ),
        .i_yummy1_2             (l_i_yummy1_2             ),

        .i_data0_3              (l_i_data0_3              ),
        .i_valid0_3             (l_i_valid0_3             ),
        .o_yummy0_3             (l_o_yummy0_3             ),
        .o_data0_3              (l_o_data0_3              ),
        .o_valid0_3             (l_o_valid0_3             ),
        .i_yummy0_3             (l_i_yummy0_3             ),

        .i_data1_3              (l_i_data1_3              ),
        .i_valid1_3             (l_i_valid1_3             ),
        .o_yummy1_3             (l_o_yummy1_3             ),
        .o_data1_3              (l_o_data1_3              ),
        .o_valid1_3             (l_o_valid1_3             ),
        .i_yummy1_3             (l_i_yummy1_3             ),

        .i_data0_4              (l_i_data0_4              ),
        .i_valid0_4             (l_i_valid0_4             ),
        .o_yummy0_4             (l_o_yummy0_4             ),
        .o_data0_4              (l_o_data0_4              ),
        .o_valid0_4             (l_o_valid0_4             ),
        .i_yummy0_4             (l_i_yummy0_4             ),

        .i_data1_4              (l_i_data1_4              ),
        .i_valid1_4             (l_i_valid1_4             ),
        .o_yummy1_4             (l_o_yummy1_4             ),
        .o_data1_4              (l_o_data1_4              ),
        .o_valid1_4             (l_o_valid1_4             ),
        .i_yummy1_4             (l_i_yummy1_4             ),
        //add
        .i_data0_5              (l_i_data0_5              ),
        .i_valid0_5             (l_i_valid0_5             ),
        .o_yummy0_5             (l_o_yummy0_5            ),
        .o_data0_5              (l_o_data0_5              ),
        .o_valid0_5             (l_o_valid0_5             ),
        .i_yummy0_5             (l_i_yummy0_5             ),

        .i_data1_5              (l_i_data1_5              ),
        .i_valid1_5             (l_i_valid1_5             ),
        .o_yummy1_5             (l_o_yummy1_5             ),
        .o_data1_5              (l_o_data1_5              ),
        .o_valid1_5             (l_o_valid1_5             ),
        .i_yummy1_5             (l_i_yummy1_5             )



    );
    aib_pair_behav #(
        .MW (640 )
    ) u_aib_pair_behav(
    	.clk          (mclk          ),
        .rst          (rst          ),
        .l_data_in_f  (l_data_in_f  ),
        .l_data_out_f (l_data_out_f ),
        .r_data_in_f  (r_data_in_f  ),
        .r_data_out_f (r_data_out_f )
    );
    aib_mac_ch r_aib_mac_ch(
        .mclk(mclk),
        .nclk(nclk),
        .rst                    (rst                    ),
        .CX                    (R_CX                   ),
        .CY                    (R_CY                   ),
        .data_in_f              (r_data_in_f              ),
        .data_out_f             (r_data_out_f             ),
        .m_wr_clk               (r_m_wr_clk               ),
        .m_rd_clk               (r_m_rd_clk               ),
        .m_ns_fwd_clk           (r_m_ns_fwd_clk           ),
        .m_fs_fwd_clk           (r_m_fs_fwd_clk           ),
        .ns_mac_rdy             (r_ns_mac_rdy             ),
        .fs_mac_rdy             (r_fs_mac_rdy             ),
        .ns_adapter_rstn        (r_ns_adapter_rstn        ),
        .ms_tx_dcc_dll_lock_req (r_ms_tx_dcc_dll_lock_req ),
        .ms_rx_dcc_dll_lock_req (r_ms_rx_dcc_dll_lock_req ),
        .sl_tx_dcc_dll_lock_req (r_sl_tx_dcc_dll_lock_req ),
        .sl_rx_dcc_dll_lock_req (r_sl_rx_dcc_dll_lock_req ),
        .ms_tx_transfer_en      (r_ms_tx_transfer_en      ),
        .ms_rx_transfer_en      (r_ms_rx_transfer_en      ),
        .sl_tx_transfer_en      (r_sl_tx_transfer_en      ),
        .sl_rx_transfer_en      (r_sl_rx_transfer_en      ),
        .i_data0_0              (r_i_data0_0              ),
        .i_valid0_0             (r_i_valid0_0             ),
        .o_yummy0_0             (r_o_yummy0_0             ),
        .o_data0_0              (r_o_data0_0              ),
        .o_valid0_0             (r_o_valid0_0             ),
        .i_yummy0_0             (r_i_yummy0_0             ),
        .i_data1_0              (r_i_data1_0              ),
        .i_valid1_0             (r_i_valid1_0             ),
        .o_yummy1_0             (r_o_yummy1_0             ),
        .o_data1_0              (r_o_data1_0              ),
        .o_valid1_0             (r_o_valid1_0             ),
        .i_yummy1_0             (r_i_yummy1_0             ),
        .i_data0_1              (r_i_data0_1              ),
        .i_valid0_1             (r_i_valid0_1             ),
        .o_yummy0_1             (r_o_yummy0_1             ),
        .o_data0_1              (r_o_data0_1              ),
        .o_valid0_1             (r_o_valid0_1             ),
        .i_yummy0_1             (r_i_yummy0_1             ),
        .i_data1_1              (r_i_data1_1              ),
        .i_valid1_1             (r_i_valid1_1             ),
        .o_yummy1_1             (r_o_yummy1_1             ),
        .o_data1_1              (r_o_data1_1              ),
        .o_valid1_1             (r_o_valid1_1             ),
        .i_yummy1_1             (r_i_yummy1_1             ),
        .i_data0_2              (r_i_data0_2              ),
        .i_valid0_2             (r_i_valid0_2             ),
        .o_yummy0_2             (r_o_yummy0_2             ),
        .o_data0_2              (r_o_data0_2              ),
        .o_valid0_2             (r_o_valid0_2             ),
        .i_yummy0_2             (r_i_yummy0_2             ),
        .i_data1_2              (r_i_data1_2              ),
        .i_valid1_2             (r_i_valid1_2             ),
        .o_yummy1_2             (r_o_yummy1_2             ),
        .o_data1_2              (r_o_data1_2              ),
        .o_valid1_2             (r_o_valid1_2             ),
        .i_yummy1_2             (r_i_yummy1_2             ),
        .i_data0_3              (r_i_data0_3              ),
        .i_valid0_3             (r_i_valid0_3             ),
        .o_yummy0_3             (r_o_yummy0_3             ),
        .o_data0_3              (r_o_data0_3              ),
        .o_valid0_3             (r_o_valid0_3             ),
        .i_yummy0_3             (r_i_yummy0_3             ),
        .i_data1_3              (r_i_data1_3              ),
        .i_valid1_3             (r_i_valid1_3             ),
        .o_yummy1_3             (r_o_yummy1_3             ),
        .o_data1_3              (r_o_data1_3              ),
        .o_valid1_3             (r_o_valid1_3             ),
        .i_yummy1_3             (r_i_yummy1_3             ),
        .i_data0_4              (r_i_data0_4              ),
        .i_valid0_4             (r_i_valid0_4             ),
        .o_yummy0_4             (r_o_yummy0_4             ),
        .o_data0_4              (r_o_data0_4              ),
        .o_valid0_4             (r_o_valid0_4             ),
        .i_yummy0_4             (r_i_yummy0_4             ),
        .i_data1_4              (r_i_data1_4              ),
        .i_valid1_4             (r_i_valid1_4             ),
        .o_yummy1_4             (r_o_yummy1_4             ),
        .o_data1_4              (r_o_data1_4              ),
        .o_valid1_4             (r_o_valid1_4             ),
        .i_yummy1_4             (r_i_yummy1_4             ),
            //add
        .i_data0_5              (r_i_data0_5              ),
        .i_valid0_5             (r_i_valid0_5             ),
        .o_yummy0_5             (r_o_yummy0_5            ),
        .o_data0_5              (r_o_data0_5              ),
        .o_valid0_5             (r_o_valid0_5             ),
        .i_yummy0_5             (r_i_yummy0_5             ),

        .i_data1_5              (r_i_data1_5              ),
        .i_valid1_5             (r_i_valid1_5             ),
        .o_yummy1_5             (r_o_yummy1_5             ),
        .o_data1_5              (r_o_data1_5              ),
        .o_valid1_5             (r_o_valid1_5             ),
        .i_yummy1_5             (r_i_yummy1_5             )
    );
    initial begin
        $dumpfile("aib_mac_ch_tb.vcd");
        $dumpvars;
        L_CX=1;
        L_CY=1;
        R_CX=2;
        R_CY=1;
        mclk=1;
        forever #40 mclk=~mclk;
    end
    initial begin
        nclk=1;
        forever #13 nclk=~nclk;
    end
    initial begin
        repeat(1000) @(posedge nclk);
        $display("timeout");
        $finish;
    end
    initial begin
        rst=1;
        repeat(5) @(negedge mclk);
            rst=0;
    end
    
    // TEMPLATE
    // router_behav #(
    //     .IR (IR ),
    //     .ER (ER )
    // ) router_behav_$R$I$S(
    // 	.clk     (clk     ),
    //     .rst     (rst     ),
    //     .o_valid ($R_i_valid$S_$I ),
    //     .o_data  ($R_i_data$S_$I  ),
    //     .i_yummy ($R_o_yummy$S_$I ),
    //     .i_valid ($R_o_valid$S_$I ),
    //     .i_data  ($R_o_data$S_$I  ),
    //     .o_yummy ($R_i_yummy$S_$I )
    // );
    localparam IR = 70;
    localparam ER = 50;
    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l00(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid0_0 ),
        .o_data  (l_i_data0_0  ),
        .i_yummy (l_o_yummy0_0 ),
        .i_valid (l_o_valid0_0 ),
        .i_data  (l_o_data0_0  ),
        .o_yummy (l_i_yummy0_0 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l01(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid1_0 ),
        .o_data  (l_i_data1_0  ),
        .i_yummy (l_o_yummy1_0 ),
        .i_valid (l_o_valid1_0 ),
        .i_data  (l_o_data1_0  ),
        .o_yummy (l_i_yummy1_0 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l10(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid0_1 ),
        .o_data  (l_i_data0_1  ),
        .i_yummy (l_o_yummy0_1 ),
        .i_valid (l_o_valid0_1 ),
        .i_data  (l_o_data0_1  ),
        .o_yummy (l_i_yummy0_1 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l11(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid1_1 ),
        .o_data  (l_i_data1_1  ),
        .i_yummy (l_o_yummy1_1 ),
        .i_valid (l_o_valid1_1 ),
        .i_data  (l_o_data1_1  ),
        .o_yummy (l_i_yummy1_1 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l20(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid0_2 ),
        .o_data  (l_i_data0_2  ),
        .i_yummy (l_o_yummy0_2 ),
        .i_valid (l_o_valid0_2 ),
        .i_data  (l_o_data0_2  ),
        .o_yummy (l_i_yummy0_2 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l21(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid1_2 ),
        .o_data  (l_i_data1_2  ),
        .i_yummy (l_o_yummy1_2 ),
        .i_valid (l_o_valid1_2 ),
        .i_data  (l_o_data1_2  ),
        .o_yummy (l_i_yummy1_2 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l30(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid0_3 ),
        .o_data  (l_i_data0_3  ),
        .i_yummy (l_o_yummy0_3 ),
        .i_valid (l_o_valid0_3 ),
        .i_data  (l_o_data0_3  ),
        .o_yummy (l_i_yummy0_3 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l31(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid1_3 ),
        .o_data  (l_i_data1_3  ),
        .i_yummy (l_o_yummy1_3 ),
        .i_valid (l_o_valid1_3 ),
        .i_data  (l_o_data1_3  ),
        .o_yummy (l_i_yummy1_3 )
    );

    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l40(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid0_4 ),
        .o_data  (l_i_data0_4  ),
        .i_yummy (l_o_yummy0_4 ),
        .i_valid (l_o_valid0_4 ),
        .i_data  (l_o_data0_4  ),
        .o_yummy (l_i_yummy0_4 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_l41(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (l_i_valid1_4 ),
        .o_data  (l_i_data1_4  ),
        .i_yummy (l_o_yummy1_4 ),
        .i_valid (l_o_valid1_4 ),
        .i_data  (l_o_data1_4  ),
        .o_yummy (l_i_yummy1_4 )
    );

    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r00(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid0_0 ),
        .o_data  (r_i_data0_0  ),
        .i_yummy (r_o_yummy0_0 ),
        .i_valid (r_o_valid0_0 ),
        .i_data  (r_o_data0_0  ),
        .o_yummy (r_i_yummy0_0 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r01(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid1_0 ),
        .o_data  (r_i_data1_0  ),
        .i_yummy (r_o_yummy1_0 ),
        .i_valid (r_o_valid1_0 ),
        .i_data  (r_o_data1_0  ),
        .o_yummy (r_i_yummy1_0 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r10(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid0_1 ),
        .o_data  (r_i_data0_1  ),
        .i_yummy (r_o_yummy0_1 ),
        .i_valid (r_o_valid0_1 ),
        .i_data  (r_o_data0_1  ),
        .o_yummy (r_i_yummy0_1 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r11(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid1_1 ),
        .o_data  (r_i_data1_1  ),
        .i_yummy (r_o_yummy1_1 ),
        .i_valid (r_o_valid1_1 ),
        .i_data  (r_o_data1_1  ),
        .o_yummy (r_i_yummy1_1 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r20(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid0_2 ),
        .o_data  (r_i_data0_2  ),
        .i_yummy (r_o_yummy0_2 ),
        .i_valid (r_o_valid0_2 ),
        .i_data  (r_o_data0_2  ),
        .o_yummy (r_i_yummy0_2 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r21(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid1_2 ),
        .o_data  (r_i_data1_2  ),
        .i_yummy (r_o_yummy1_2 ),
        .i_valid (r_o_valid1_2 ),
        .i_data  (r_o_data1_2  ),
        .o_yummy (r_i_yummy1_2 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r30(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid0_3 ),
        .o_data  (r_i_data0_3  ),
        .i_yummy (r_o_yummy0_3 ),
        .i_valid (r_o_valid0_3 ),
        .i_data  (r_o_data0_3  ),
        .o_yummy (r_i_yummy0_3 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r31(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid1_3 ),
        .o_data  (r_i_data1_3  ),
        .i_yummy (r_o_yummy1_3 ),
        .i_valid (r_o_valid1_3 ),
        .i_data  (r_o_data1_3  ),
        .o_yummy (r_i_yummy1_3 )
    );

    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r40(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid0_4 ),
        .o_data  (r_i_data0_4  ),
        .i_yummy (r_o_yummy0_4 ),
        .i_valid (r_o_valid0_4 ),
        .i_data  (r_o_data0_4  ),
        .o_yummy (r_i_yummy0_4 )
    );


    router_behav #(
        .IR (IR ),
        .ER (ER )
    ) router_behav_r41(
        .clk     (nclk     ),
        .rst     (rst     ),
        .o_valid (r_i_valid1_4 ),
        .o_data  (r_i_data1_4  ),
        .i_yummy (r_o_yummy1_4 ),
        .i_valid (r_o_valid1_4 ),
        .i_data  (r_o_data1_4  ),
        .o_yummy (r_i_yummy1_4 )
    );

    // TEMPLATE
    always @(posedge nclk) begin
        if(l_i_valid0_0)
            $display("%t:l00i:%h",$time,l_i_data0_0);
        if(l_o_valid0_0)
            $display("%t:l00o:%h",$time,l_o_data0_0);
    end
    always @(posedge nclk) begin
        if(l_i_valid1_0)
            $display("%t:l01i:%h",$time,l_i_data1_0);
        if(l_o_valid1_0)
            $display("%t:l01o:%h",$time,l_o_data1_0);
    end
    always @(posedge nclk) begin
        if(r_i_valid0_0)
            $display("%t:r00i:%h",$time,r_i_data0_0);
        if(r_o_valid0_0)
            $display("%t:r00o:%h",$time,r_o_data0_0);
    end
    always @(posedge nclk) begin
        if(r_i_valid1_0)
            $display("%t:r01i:%h",$time,r_i_data1_0);
        if(r_o_valid1_0)
            $display("%t:r01o:%h",$time,r_o_data1_0);
    end

    always @(posedge nclk) begin
        if(l_i_valid0_1)
            $display("%t:l10i:%h",$time,l_i_data0_1);
        if(l_o_valid0_1)
            $display("%t:l10o:%h",$time,l_o_data0_1);
    end
    always @(posedge nclk) begin
        if(l_i_valid1_1)
            $display("%t:l11i:%h",$time,l_i_data1_1);
        if(l_o_valid1_1)
            $display("%t:l11o:%h",$time,l_o_data1_1);
    end
    always @(posedge nclk) begin
        if(r_i_valid0_1)
            $display("%t:r10i:%h",$time,r_i_data0_1);
        if(r_o_valid0_1)
            $display("%t:r10o:%h",$time,r_o_data0_1);
    end
    always @(posedge nclk) begin
        if(r_i_valid1_1)
            $display("%t:r11i:%h",$time,r_i_data1_1);
        if(r_o_valid1_1)
            $display("%t:r11o:%h",$time,r_o_data1_1);
    end

    always @(posedge nclk) begin
        if(l_i_valid0_2)
            $display("%t:l20i:%h",$time,l_i_data0_2);
        if(l_o_valid0_2)
            $display("%t:l20o:%h",$time,l_o_data0_2);
    end
    always @(posedge nclk) begin
        if(l_i_valid1_2)
            $display("%t:l21i:%h",$time,l_i_data1_2);
        if(l_o_valid1_2)
            $display("%t:l21o:%h",$time,l_o_data1_2);
    end
    always @(posedge nclk) begin
        if(r_i_valid0_2)
            $display("%t:r20i:%h",$time,r_i_data0_2);
        if(r_o_valid0_2)
            $display("%t:r20o:%h",$time,r_o_data0_2);
    end
    always @(posedge nclk) begin
        if(r_i_valid1_2)
            $display("%t:r21i:%h",$time,r_i_data1_2);
        if(r_o_valid1_2)
            $display("%t:r21o:%h",$time,r_o_data1_2);
    end

    always @(posedge nclk) begin
        if(l_i_valid0_3)
            $display("%t:l30i:%h",$time,l_i_data0_3);
        if(l_o_valid0_3)
            $display("%t:l30o:%h",$time,l_o_data0_3);
    end
    always @(posedge nclk) begin
        if(l_i_valid1_3)
            $display("%t:l31i:%h",$time,l_i_data1_3);
        if(l_o_valid1_3)
            $display("%t:l31o:%h",$time,l_o_data1_3);
    end
    always @(posedge nclk) begin
        if(r_i_valid0_3)
            $display("%t:r30i:%h",$time,r_i_data0_3);
        if(r_o_valid0_3)
            $display("%t:r30o:%h",$time,r_o_data0_3);
    end
    always @(posedge nclk) begin
        if(r_i_valid1_3)
            $display("%t:r31i:%h",$time,r_i_data1_3);
        if(r_o_valid1_3)
            $display("%t:r31o:%h",$time,r_o_data1_3);
    end

    always @(posedge nclk) begin
        if(l_i_valid0_4)
            $display("%t:l40i:%h",$time,l_i_data0_4);
        if(l_o_valid0_4)
            $display("%t:l40o:%h",$time,l_o_data0_4);
    end
    always @(posedge nclk) begin
        if(l_i_valid1_4)
            $display("%t:l41i:%h",$time,l_i_data1_4);
        if(l_o_valid1_4)
            $display("%t:l41o:%h",$time,l_o_data1_4);
    end
    always @(posedge nclk) begin
        if(r_i_valid0_4)
            $display("%t:r40i:%h",$time,r_i_data0_4);
        if(r_o_valid0_4)
            $display("%t:r40o:%h",$time,r_o_data0_4);
    end
    always @(posedge nclk) begin
        if(r_i_valid1_4)
            $display("%t:r41i:%h",$time,r_i_data1_4);
        if(r_o_valid1_4)
            $display("%t:r41o:%h",$time,r_o_data1_4);
    end

endmodule